1. Field of the Invention
The present invention relates to semiconductor inspecting apparatus used to inspect a semiconductor wafer, and more specifically to a semiconductor inspecting apparatus such as a wafer prober apparatus for inspecting electric characteristics of semiconductor chips (e.g., product chips and TEG (test element group) chips) arranged repeatedly on a semiconductor wafer.
2. Description of the Prior Art
On a semiconductor wafer, a plurality of product chips manufactured as products are formed and arranged repeatedly. These product chips are manufactured by exposing one product chip or a plurality of product chips in a single step. Further, the product chips are provided whenever the semiconductor wafer is moved, to manufacture the product chips all over the surface of the semiconductor wafer.
Further, all the manufactured product chips are 100%-tested on the semiconductor wafer individually by use of a semiconductor inspecting apparatus. The inspection results, that is, the defectiveness or the non-defectiveness is recorded for each product chip for each predetermined inspection item.
The prior art method of inspecting the semiconductor wafer by use of a prober apparatus will be explained hereinbelow with reference to the attached drawings.
FIG. 4 shows two product chips A and B each having a horizontal chip size of "a" and a vertical chip size of "b", and FIG. 7 shows a semiconductor wafer 1 on which a plurality of these product chips A and B are arranged. In FIG. 7, the product chips A and the product chips B are printed simultaneously on the same semiconductor wafer 1 at a single printing step. Here, although the two product chips A and B are different from each other, since the chip sizes "a" and "b" are equal to each other, these two chips can be considered as being equivalent to each other when inspected.
FIG. 1 shows a conventional stage control section. In FIG. 1, the horizontal chip size "a" and the vertical chip size "b" of the product chips A and B as shown in FIG. 4 are registered in an x-index section 31 and a y-index section 32, respectively. Further, the number and the arrangement order of product chips A and B (two chips in the case shown in FIG. 7) inspected at the same time are registered in a simultaneous inspection commanding section 33.
An X/Y control section 34 generates two movement control signals for controlling the movements of a chuck stage 2 on the basis of data inputted by the x-index section 31, the y-index section 32, and the simultaneous inspection commanding section 33. The two generated control signals are inputted to an X motor driving section 35 and a Y motor driving section 36, respectively. On the basis of these two movement control signals, the X motor driving section 35 and the Y motor driving section 36 control the movements of the chuck stage 2 in both the x-axis and y-axis directions.
The maximum movement distances are determined for the chuck stage 2. Therefore, within the maximum movement distances, the product chips must be arranged repeatedly on the semiconductor wafer 1.
An XADDR section 38 and a YADDR section 39 add index units (i.e., the movement units) of the chuck stage 2 in both x-axis and y-axis directions, respectively, and command the added results to an X/Y control section 34, respectively.
As a result, as shown in FIG. 7, it is possible to give the horizontal coordinate values of ax1 to ax6 and the vertical coordinate values of ay1 to ay6 to the product chips, in both the horizontal x-axis and the vertical y-axis directions, respectively. Here, since the movable range of the chuck stage 2 is divided into a lattice pattern in indexed units, each of the product chips can be allocated on the basis of the x-coordinate value and the y-coordinate value given to each section of the lattice pattern, respectively.
Further, the chuck stage 2 and the semiconductor wafer 1 are aligned in such a way that the movement directions of the chuck stage 2 match the arrangement directions of the lattice pattern of the semiconductor wafer 1 in both the directions. Further, after the alignment, five product chips 71 to 75 distributing as shown in FIG. 10 are all checked to determine whether these product chips have the same index unit or not. By this check, it is possible to confirm the alignment of both the x-axis and y-axis directions and further the chip size. Further, in FIG. 10, although the product chip (A) 72 is different from the other four product chips (B) 71, 73, 74 and 75 with respect to the contents of one shot, since the chip sizes of both the product chips A and B are the same with respect to each other, it is possible to align these two product chips A and B without causing any problems.
FIG. 12 shows an example of the movements of the chuck stage 2 after the alignment. The chuck stage 2 is controllably moved in unit of one chip size regularly beginning from a start point (1) (i.e., a product chip 52), through (2), (3), . . . (14), (15), to the last point (16). These movement control can be executed by the XADDR section 38 and the YADDR section 39, by adding each unit of the chip sizes "a" and "b" in both the x-axis and y-axis directions, respectively.
In more detail, when the product chip 52 is moved in one index unit from the product chip 52 (X:ax3; Y:ay1) to the product chip 53 (X:ax4; Y:ay1) in the x-axis direction, the X-coordinate of each product chip changes by one index unit. In the same way, when the product chip 52 is moved in one index unit in the y-axis direction, the Y-axis coordinate of each product changes by one index unit.
Whenever the respective product chip is moved by the chuck stage relative to each inspection position by the prober, the electric characteristics of the product chip are measured. The inspection results (i.e., a non-defective products or a defective product) are stored in a memory for each product chip in combination with the coordinates of the product chips.
Further, a plurality of the product chips are measured at the same time as follows:
FIG. 14 shows an example of the operation for measuring two product chips at the same time. In this example, since two probers are arranged and further moved simultaneously, it is possible to measure the electric characteristics of the two product chips 52 and 53 at the same time. The stage 2 is moved from the product chip 52 (i.e., the starting point (1)) to the product chip 54 (i.e., the succeeding point(2)).
Here, since only one coordinate value is registered in each of the XADDR section 38 and the YADDR section 39, respectively, it is possible to index another chip coordinate relatively on the basis of the data given by the simultaneous measurement commanding section 33.
In the example shown in FIG. 14, it is registered in the simultaneous measurement commanding section 33 that there are two product chips to be measured at the same time relative to the product chip 52 located at the reference position and further that one (e.g. 53) of the two product chips measured at the same time is located on the right side of the other (e.g., 52) of the two product chips.
In response to the commands of the simultaneous measurement commanding section 33, the X/Y control section 34 moves the chuck stage 2 in block unit obtained by grouping a plurality of the simultaneous measurements (two in the case shown in FIG. 4) as one block, because the two chips are grouped as one block in this example.
The measurement results are stored in the memory in combination with the coordinates of each chip, in the same way as when the chips are measured one by one.
FIG. 16 shows an example of the movements of the chuck stage, when six product chips (two in the x-axis direction and three in the y-axis direction) are measured at the same time.
In this example, when the simultaneous measurement is registered by setting the product chip 52 (132) as the reference chip, the stage is moved to the lattice areas 131 and 132 in which the product chips are not formed in practice. Further, in this example, both the XADDR section 38 and the YADDR section 39 designate the coordinates of the two lattice areas 131 and 133 where no practical product chips are formed. In the same way as with the case of the two simultaneous measurements, individual coordinates are allocated to each of the remaining five product chips on the basis of the coordinates of the reference product chip (e.g., 52).
The measurement results are stored in the memory in combination with the coordinates of each product chip, in the same way as when the product chips are measured one by one.
FIG. 19 shows the case where six product chips arranged in a y-axis line are measured at the same time. The simultaneous measurements are basically the same as with the case where the product chips are measured one by one, or two by two, or six (=2.times.3) by six, so that any detailed description thereof is omitted herein.
FIG. 20 shows an example of the operation for printing a defective mark (e.g., ink mark) on each of the product chips registered as being defective after the end of the electrical measurements. In more detail, when the final product chip has been measured, the prober prints a mark on each of defective chip in the order of the registered defective chip data. In FIG. 20, since four defective chips 171, 172, 173 and 174 are found, the prober is moved to print a defective mark (i.e., an ink mark) in the order of (1), (2), (3) and (4).
FIG. 22 shows a prior art flowchart of controllably moving the chuck stage 2. By this flowchart, it is possible to decide the movement to the succeeding product chip and the number of chips to be moved. In more detail, in FIG. 22, the flowchart starts from A! to move the chuck stage 2. In step ST10, if the present chip is not the final chip arranged in a row, in step ST11 the stage is moved by one index (one chip), and this subroutine ends at B!. However, in step ST10, if the present chip is the final chip arranged in a row, in step ST12 the succeeding column is discriminated. If the discriminated column is the final column, since this indicates the final chip, the stage is not moved, ending the subroutine.
However, in step ST12, if the chip is arranged in a column other than the final column, in step ST13 the prober is moved to the succeeding chip, and row movement data n is loaded. Further, in step ST14, the column is moved by one index and further the row is indexed by n indices. Further, the movement direction is reversed and then the same procedure as above is repeated. When the prober movement ends, the subroutine ends at B!.
By the way, in order to inspect whether the product chips are defective or not during the manufacturing process, so-called TEG (test element group) chips are sometime formed and arranged in addition to the product chips. These TEG chips can achieve an important role, in particular at the early stage of development of the semiconductor device, because the production technology for newly developed product chips has not yet been established sufficiently or perfectly. The TEG chips must be formed on the semiconductor wafer at each step, whenever the product chips are manufactured.
FIG. 5 shows an example of the arrangement in which one product chip A and one TEG chip are printed at the same step. The horizontal width of the product chip A is "a", and the horizontal width of the TEG chip T is "c" which is different from "a". In the prior art method, as already explained, it has been necessary to arrange the TEG chips T in one-to-one correspondence to the product chips T, as shown in FIG. 5. This is because in the prior art wafer prober apparatus, the chuck stage 2 can be moved only in unit of one index. Therefore, in the prior art method, only when the TEG chips T and the product chips A are arranged adjacent to each other in one-to-one correspondence relationship with respect to each other or only when one product chip A and one TEG chip T are formed at the same step, the product chips A can be inspected.
In other words, in the prior art method, since the TEG chips T and the product chips A must be arranged adjacent to each other in one-to-one correspondence relationship as shown in FIG. 5, there exists a problem in that a great number of TEG chips must be formed on the semiconductor wafer.
Further, when one TEG chip T and a plurality of product chips A are formed at the same step as shown in FIG. 6, it has been so far impossible to inspect a plurality of the product chips by use of the prior art wafer prober apparatus.
Therefore, when a great number of TEG chips are arranged, after the production technology of the newly-developed chips has been established perfectly, there arises a problem in that the number of the product chips is inevitably reduced, because the product chips are formed in a narrowed area on the same semiconductor wafer. For instance, in the case shown in FIG. 5, roughly twice the area is required for the TEG chips, as compared with the case as shown in FIG. 6. Further, the number of the steps required to form a predetermined number of product chips is also doubled.
Recently, however, there exists such a tendency that the size of the product chips increases. Therefore, there exists a need of increasing the area usable for forming the product chips in a limited area on a semiconductor wafer, while decreasing the area occupied by the TEG chips.
Further, in the prior art method, when the TEG chips 64 are formed as shown in FIG. 9, since the shot area increases on the semiconductor wafer, the number of the product chips 52 and 53 to be formed on the semiconductor wafer decreases, as compared with the case where the TEG chips are not formed as shown in FIG. 7. For instance, when the two cases shown in FIGS. 7 and 9 are compared with each other, there exists a difference of four chips between the two. In other words, since the number of chips that can be formed on a semiconductor wafer decreases, the number of the semiconductor wafers required to manufacture a predetermined number of product chips increases. In addition, since all the TEG chips 64 are not effective, that is, since the inspection data cannot be obtained at both the right and left ends of the chips, there exists a problem in that the inspection results cannot be analyzed perfectly.
Further, to overcome these problems, it is necessary to form a plurality of product chips A and one TEG chip T at the same step, as shown in FIG. 6, to minimize an increase of area required to form the TEG chips T. In addition, it is necessary to allow the wafer prober apparatus itself to inspect the product chips formed as shown in FIG. 6.
FIG. 6 shows the example where one block composed of two product chips A and one TEG chip T are formed at the same one step, in which the size of one step is determined as a dimension of (a+b+c) in the x-axis direction. Therefore, in this example, the dimension required for one TEG chip can be decreased by half. Further, when m-units of product chips A and one TEG chip T are formed at the same one step, it is possible to decrease the dimension required to form the TEG chip by 1/m.